The present invention relates to FIFO buffers generally and, more particularly, to a clocking scheme for allowing a contiguous memory array to be used to read and write various width data words from a memory array.
A first-in first-out(FIFO) buffer reads various size data words from a memory array and writes various size data words to a memory array. In previous approaches a shift register scheme is generally required to generate a number of intermediate signals necessary to read or write a fixed data word width into the memory array. To implement a clocking scheme that retrieves fixed width data words that are equal to the width of the individual cells in the FIFO memory array, a 16-bit shift register would be required. To extend the previous approach to a memory array that is twice as wide as the width of the output data word, a 32-bit shift register would be required. Specifically, a 32-bit shift register would be necessary for a 9-bit word design and a 16-bit shift register would be required for a 18-bit word design. Previous approaches did not allow a single shift register to be used for both the 9-bit and 18-bit devices. Previous approaches for implementing FIFOs used a xe2x80x9ccarouselxe2x80x9d type data retrieval scheme that used a 16-bit shift register to directly control each of the section control signals. To extend the previous approach systems to read both a 9-bit and 18-bit word would require a 32-bit shift register. The implementation of a 32-bit shift register would cause extreme difficulty in routing the various signals to appropriately connect the outputs of the shift register to each of the section control blocks. The implementation of a 32-bit shift register would also consume more than twice the amount of chip area as compared to a 16-bit shift register. Similar shift register implementations would be required to write data to the memory array.
Referring to FIG. 1, one scheme 10 for reading multiple width digital words from a memory array is shown. The scheme 10 generally comprising a shift register 12, a set of sense amplifiers 14a, 14b, 14c and 14d and a set of memory arrays 16a, 16b, 16c and 16d. A single data output 18 represents an output that receives information presented from each of the sense amplifiers 14a-14d. The 16-bit shift register 12 presents one of a set of control inputs 20a, 20b, 20c and 20d to each of the sense amplifiers 14a-14d. When one of the control inputs 20a-20d are present at one of the sense amplifiers 14a-14d, the information presented to the data output 18 is received from the appropriate memory array 16a-16d. An individual control input 20a-20d is required for each of the memory arrays 16a-16d. As the number of memory arrays 16a-16d increases, the number of control inputs 20a-20d will also increase. Each of the control inputs 20a-20d need to be individually routed from the individual sense amplifiers 14a-14d to the shift register 12. The routing necessary to appropriately connect the control inputs 20a-20d between the shift register 12 and the sense amplifiers 14a-14d increases. To expand the shift register 12 to a 32-bit shift register would require twice the amount of routing as well as an increased amount of chip real estate. The increase in routing the control inputs 20a-20d and the increased chip area makes the previous scheme difficult to implement with multiple width data words. This problem is further discussed in co-pending application Ser. No. 08/584,530, hereby incorporated by reference in its entirety.
Referring to FIG. 2, a scheme 22 for writing multiple width digital words to a memory array is shown generally comprising a shift register 24, a set of multiplexers 26a, 26b, 26c and 26d and a set of memory arrays 28a, 28b, 28c and 28d. A single data input 30 presents an input to each of the multiplexers 26a-26d. The 16-bit shift register 24 presents one of a set of control inputs 32a, 32b, 32c and 32d to each of the multiplexers 26a-26d. When one of the control inputs 32a-32d is present at one of the multiplexers 26a-26d, the data input 30 is received and is written to the appropriate one of the memory arrays 28a-28d. Individual control inputs 32a-32d are required for each memory array 28a-28d. As the number of memory arrays 28a-28d increases, the number of control inputs 32a-32d will also increase. Each of the control inputs 32a-32d would need to be individually routed from the individual multiplexers 26a-26d to the shift register 24. The routing necessary to appropriately connect the control inputs 32a-32d between the shift register 24 and the multiplexers 26a-26d increases. To expand the shift register 24 to a 32-bit shift register would require twice the amount of routing as well as an increased amount of chip real estate. The increase in routing the control inputs 32a-32d and the increased chip area makes the previous approach difficult to implement with multiple width data words. This problem is also addressed in co-pending application Ser. No. 08/559,983, hereby incorporated by reference in its entirety.
It is desirable to receive a particular size data word from the data input 30, write the word into the memory array 28a-28d, read a different size data word from the memory array 28a-28d and then present the different sized word to the data output 18. The schemes 10 and 22 do not contemplate this multiple size word writing and reading. In particular, the chip real estate problems inherent in implementing the shift register 12 and the shift register 24 would be magnified when implementing a system that writes in a particular size digital word and reads out a different size digital word. Additionally, logic would be necessary to synchronize the writing and reading from the memory arrays 16a-16c or the memory arrays 28a-28d. It should be noted that the memory arrays 16a-16c in FIG. 1 would correspond to the memory arrays 28a-28d in FIG. 2 for a system that writes and reads different sized words.
The present invention provides a clocking scheme for receiving a particular sized data word from a common input, writing the word to a number of individual memory cells in a memory array, reading another particular sized data word from the individual memory cells and then presenting the data word to a common output. The size of the word written to the memory cells can be larger, smaller or the same as the size of the word read from the memory array. The present invention uses a multi-bit write counter to distribute a write timing signal to a number of multiplexer blocks and a multi-bit read counter to distribute a read timing signal to a number of sense amplifier blocks. Each of the multiplexer blocks receives both a data input signal from the common input and the write timing signal at all times. When a particular write timing signal is present at the multiplexer, the fixed width data input is presented to the corresponding memory array. Each of the sense amplifier blocks reads data from the memory array and receives a read timing signal at all times. When a particular read timing signal is present at a sense amplifier, the output signal containing a fixed width data word is read from one or more of the corresponding memory arrays and is presented to the common output. The present invention reduces the number of internal signal lines necessary to implement the control function and allows for easy modification to both read and write multiple width words from the memory array.
The objects, features and advantages of the present invention include providing a control circuit for distributing data to a number of memory arrays from a common input, reading data from a number of memory arrays and presenting the data to a common output for use with both synchronous and asynchronous FIFOs as well as other memory devices. The present circuit produces the distributing and reading effects using a minimum number of signal lines and eliminates the need to use wide bit shift registers. Thus, the present invention consumes less overall chip real estate. The present circuit can also be very easily adapted to larger or smaller memory organization systems with minimum design changes and can easily be adapted to denser and wider memory devices with multiple data input and output word widths.